Edveon Technologies is hiring fresh engineering graduates for the Design Verification Trainee role in Chennai. Candidates from the 2023, 2024, 2025, and 2026 batches can apply for this opportunity. Prior VLSI or Design Verification experience is not required, making this an opportunity for engineering graduates interested in starting a career in the semiconductor industry.
The trainee program is designed to provide structured technical training and practical exposure in areas such as Digital Design, Design Verification, SystemVerilog, UVM, and semiconductor technologies. Candidates will go through assessments and structured training before being considered for full-time employment based on performance.
Edveon Trainee Off Campus Hiring 2026
| DetailsInformation | Information |
|---|---|
| Company | Edveon Technologies |
| Job Role | Design Verification Trainee |
| Qualification | B.E. / B.Tech / M.E. / M.Tech |
| Eligible Branches | ECE, EEE, CSE, IT, AI & DS, VLSI, Embedded Systems, Power Electronics |
| Experience | 0 – 1 Years |
| Freshers Eligible | Yes |
| Eligible Batches | 2023, 2024, 2025 & 2026 |
| Salary | ₹3.00 – ₹6.00 LPA (Expected) |
| Job Type | Full-Time |
| Work Mode | As per Company Requirements |
| Location | Chennai, Tamil Nadu |
| Last Date | 17 October 2026 |
| Prior VLSI Experience | Not Required |
Edveon Design Verification Trainee Job Description
Edveon is hiring Design Verification Trainees who are interested in building a career in the semiconductor and VLSI industry. Candidates do not need prior professional experience in VLSI or Design Verification. A strong foundation in aptitude, logical reasoning, digital electronics, programming, and engineering fundamentals is important for this role.
Selected candidates will undergo structured technical training delivered through EdvLearn and Edveon’s engineering team. The training is intended to develop practical knowledge in digital design and verification, SystemVerilog, UVM, analog fundamentals, and related semiconductor technologies.
Candidates who successfully complete the training and assessments may be considered for full-time employment based on their performance.
Roles and Responsibilities
- Demonstrate strong aptitude and problem-solving abilities.
- Apply logical and analytical thinking to technical problems.
- Understand and work with fundamental concepts of Digital Electronics.
- Apply programming fundamentals in languages such as C, C++, Java, or Python.
- Learn and apply new technical concepts effectively.
- Develop an understanding of VLSI and semiconductor technologies.
- Participate actively in structured technical training.
- Work on Digital Design and Verification concepts during training.
- Learn SystemVerilog and verification testbench development.
- Develop an understanding of UVM fundamentals.
- Participate in technical assessments and evaluations.
- Take ownership of assigned learning and technical activities.
- Demonstrate willingness to learn and solve technical problems.
Qualifications & Skills
- Candidates must have an engineering qualification.
- B.E. / B.Tech candidates from ECE, EEE, CSE, IT, or AI & DS can apply.
- M.E. / M.Tech candidates specializing in VLSI, Embedded Systems, or Power Electronics can apply.
- Eligible graduation years are 2023, 2024, 2025, and 2026.
- Candidates with 0–1 years of experience can apply.
- Strong aptitude and logical reasoning skills.
- Good understanding of Digital Electronics.
- Programming fundamentals in at least one language such as C, C++, Java, or Python.
- Good analytical and problem-solving abilities.
- Ability to understand and apply technical concepts logically.
- Genuine interest in VLSI and semiconductor technology.
- Willingness to learn new technologies and develop engineering skills.
- Prior VLSI or Design Verification experience is not mandatory.
Training Program
Selected candidates will undergo structured technical training delivered through EdvLearn and Edveon’s engineering team.
The training program covers:
- Digital Design & Verification
- SystemVerilog
- Verification and Testbench Development
- UVM Basics
- Analog Basics
- Semiconductor and VLSI-related concepts
Candidates will be evaluated during and after the training program. Based on assessment and performance, selected candidates may receive an opportunity for full-time employment.
Selection Process
The Edveon recruitment process consists of multiple stages:
1. Application:
Candidates submit their application for the Design Verification Trainee position.
2. Eligibility Screening:
Applications are reviewed based on educational qualifications, graduation year, branch, and other eligibility requirements.
3. Written Test:
Eligible candidates participate in a written assessment covering aptitude, logical reasoning, Digital Electronics, and programming fundamentals.
4. Technical Assessment & Interview:
Candidates who qualify the written test may proceed to technical assessment and interview rounds.
5. Structured Training:
Selected candidates undergo technical training covering Digital Design, Verification, SystemVerilog, UVM Basics, and Analog Basics.
6. Assessment:
Candidates are evaluated based on their learning and technical performance during the training program.
7. Full-Time Employment:
Candidates who successfully meet the required performance criteria may be considered for full-time employment.
Salary Details
The expected salary for the Edveon Design Verification Trainee role is approximately ₹3.00 LPA to ₹6.00 LPA.
This is an expected salary range and is not an officially disclosed compensation range in the job details provided. Actual compensation may vary depending on the employment terms, candidate performance, skills, and company policies.
How To Apply For Edveon Off Campus Hiring 2026
- Click on the Apply Here button provided below.
- Review the Design Verification Trainee eligibility criteria.
- Check your graduation year and engineering branch.
- Complete the application form with accurate details.
- Upload your updated resume and required documents.
- Submit your application before the mentioned deadline.
- Shortlisted candidates will be informed about the written test and further selection stages.
Edveon Apply Link: Click Here
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About Edveon Technologies
Edveon Technologies is a semiconductor-focused organization working on developing and preparing engineering talent for careers in VLSI and semiconductor design.
The company provides structured technical training and practical exposure in areas such as Digital Design, Design Verification, SystemVerilog, UVM, and related semiconductor technologies.
For fresh engineering graduates, Edveon provides a pathway to enter the semiconductor industry through technical training, assessments, and performance-based full-time employment opportunities. Its trainee program is designed to help candidates develop industry-relevant technical skills while gaining practical engineering exposure.
Final Summary
Edveon Technologies is hiring Design Verification Trainees for its Chennai opportunity. The opening is available for 2023, 2024, 2025, and 2026 engineering graduates with 0–1 years of experience.
Candidates with B.E./B.Tech in ECE, EEE, CSE, IT, or AI & DS, as well as M.E./M.Tech candidates in VLSI, Embedded Systems, or Power Electronics, can apply. Prior VLSI or Design Verification experience is not required.
The selection process includes eligibility screening, written test, technical assessment and interview, structured training, assessment, and potential full-time employment. The expected salary is ₹3.00–₹6.00 LPA, and the listed application expiration date is 17 October 2026.
